The present invention relates to a semiconductor memory device having an electrically programmable and erasable memory cell.
The most typical one of conventional nonvolatile semiconductor memories is a stacked flash memory using two-layered polysilicon. FIGS. 6A and 6B show the memory cell of the flash memory. In this memory cell, a floating gate 603 is formed on a semiconductor substrate 601 via a gate insulating film 602, a control gate 605 is formed on the floating gate 603 via an isolation insulating film 604, and an impurity-doped source 606 and drain 607 are formed on the two sides of the floating gate 603 in the semiconductor substrate 601.
In this memory cell, for example, data is erased by grounding the control gate 605, applying a high voltage Vpp (about 12 V) to the source 606, and extracting electrons from the floating gate 603 by an FN tunnel current between the source 606 and floating gate 603, as shown in FIG. 6A.
Data is written using hot electron injection by injecting electrons into the floating gate 603, as shown in FIG. 6B.
In this case, injecting electrons into the floating gate means "write".
The erase is generally performed by the following procedure (intelligent erase).
To prevent an over erase, data is written in all memory cells (electrons are satisfactorily injected into floating gates).
An erase using a pulse of about 10 msec and a read (erase verify) for verifying the erase are repeatedly performed until the maximum values of the thresholds (Vth) of all memory cell transistors become equal to or smaller than a predetermined voltage (about 3 V).
A write is performed by a similar procedure. A write using a write pulse of about 10 .mu.sec and a read for verifying the transistor threshold level are repeatedly performed until the maximum value of the threshold of each memory cell transistor becomes equal to or larger than a predetermined voltage (about 7 V).
FIG. 7 shows the threshold distribution of an erased/written memory cell by the above intelligent erase method. In general, the threshold is distributed in the wide ranges of 6 V or more in a written memory cell and 0.5 V to 3 V in an erased memory cell owing to variations between memory cells caused by variations in wafer manufacturing process such as the film thickness or gate length.
In the above-described memory cell structure, the threshold varies in this manner, and a write is difficult to perform so as to extract a desired voltage including variations in threshold. This interferes with realizing multilevel digital or analog memories.
FIG. 8 shows the structure of a split gate type nonvolatile memory (the structure of a memory cell). In this memory cell, a floating gate 803 is formed on a semiconductor substrate 801 via a gate insulating film 802, and a control gate 805 is formed on the floating gate 803 via an isolation insulating film 804. As the characteristic feature of the memory cell, part of the control gate 805 extends up to the gate insulating film 802 on a side of the floating gate 803. An impurity-doped source 806 is formed on a side of the control gate 805 on the gate insulating film 802 in the semiconductor substrate 801, and an impurity-doped drain 807 is formed on a side of the floating gate 803.
In this memory cell, since the extending portion of the control gate 805 functions as a select transistor, the selectivity can be maintained even if the transistor is depleted by an over erase. That is, since this structure is less susceptible to over erase, no write need be performed first, or no operation such as intelligent erase of sequentially checking the erase state need be performed. The threshold distribution can be used to a lower voltage side, and thus a value can be written in a wider voltage range.
Except for this, however, the split gate type memory is basically the same as the stacked memory described above, and analog values or multilevel digital values are also difficult to write.
As a technique for realizing a write of analog values or multilevel digital values, a pulse write method using a ramp voltage and a method of controlling a write while monitoring a reference value and a memory output by a comparator are proposed.
An example of the analog value write method using a ramp voltage will be explained. In this method, zero data is first written in all memory cells as initialization (electrons are satisfactorily injected into floating gates). A voltage is roughly sampled from a high-voltage source whose output voltage gradually changes by a pulse having a constant width (e.g., about 100 .mu.sec), and a coarse pulse is applied to the drain of a target memory cell.
At this time, the control gate is grounded to 0 V, and electrons are gradually extracted from the floating gate by an FN current. After a high voltage is applied to the drain of the memory cell for a time corresponding to the constant-width pulse, application of the high voltage for a write is stopped, and a read starts.
When the control gate and drain are set to a read voltage (5 V), a voltage corresponding to the remaining charge amount of the floating gate appears on the source side, and is read by a source follower circuit, and is compared by the comparator with a set voltage value to be written.
If the read value reached the predetermined value, the read shifts to a next fine write sequence; if the read value is smaller, a rough write voltage increased by a predetermined magnitude by a next coarse pulse is applied to the drain. This operation is repeatedly performed until the read value reaches a predetermined value (e.g., a voltage lower than the set voltage value by a predetermined magnitude). The increase in voltage is determined by a ramp voltage and the number of pulses. For example, when the ramp voltage is 11 to 21 V, and the number of pulses is 45, the step of a rough write voltage is (21-11)/45.noteq.0.22 V.
By the same method, a write and read are repeatedly performed until the read value reaches a voltage to be written by setting a high voltage for a write whose read value has reached the predetermined value with a finer voltage change gradient within a shorter application time of the high voltage for a write to the memory cell.
This method realizes a write of analog values. However, the time necessary for a write is as long as (pulse width used for one write).times.(number of pulses), e.g., 100 .mu.sec.times.45+50 .mu.sec.times.90=9.0 msec.
The technique of controlling a write while monitoring a reference value and a memory output by a comparator will be explained.
In this technique, the memory cell (circuit) is constituted as shown in FIG. 9, and "0" is written in all memory cells as initialization. A voltage to be written is set as a reference voltage in a comparator 901. In the next step, Vpp is applied to a floating gate 902 to extract electrons. The voltage of the floating gate 902 at this time is always monitored by a source follower operation. When an output value from the memory cell reaches the voltage to be written, a transistor 903 is turned on by an output from the comparator 901 to complete a write.
In this case, since a write and read need not be alternately repeated, one write time can be shortened to about 1 msec though it depends on an FN current amount. However, all memory cells must be reset as initialization before a write. In addition, a write value is monitored by a source follower operation, and a write is controlled by a feedback mechanism using the comparator to stop the operation at desired write voltage. This requires a peripheral control circuit, complicates the circuit design, and increases the chip size.
In either method, a written value is monitored by any means, and when the floating gate voltage reaches a voltage to be written, application of the programming voltage is stopped to end a write. As a result, the write time and a peripheral circuit are increased.
As described above, in the prior art, analog values or multilevel digital values are difficult to write. When analog values or multilevel digital values are to be recorded, initialization must be performed. In a flash memory having a memory capacity of about 8 MB, this initialization generally spends 1 sec or more.
Note that the memory cell may comprise a dedicated third gate 1001, as shown in FIG. 10, so as to apply a relatively high voltage in an erase in order to shorten the erase time.